Discrete Cosine Transform (DCT) is the most widely used technique in image and video compression. In this paper, the structure of DCT and Inverse DCT (IDCT) algorithm is split in the form of COordinate Rotation DIgital Computer (CORDIC) rotation matrix. The two-dimensional (2-D) 88 DCT/IDCT units based on the improved rotation CORDIC algorithm is proposed. The shift and addition operations of the CORDIC algorithm are used to replace the cosine multiplication operations in the algorithm. The design does not contain any multiplier unit, which reduces the complexity of the hardware unit. The row-column transform unit composed of register arrays connects two 1-D 8-point DCT units to complete the calculation of 2-D 88 DCT. The pipeline latency of proposed architecture is 28 clock cycles. The proposed efficient two-dimensional DCT architecture has been synthesized on the Xilinx’s Kintex-7 FPGA. The resource utilization is 17.36 % for Slice LUTs, 3.49 % for Slice Registers, and the maximum operating frequency is 172 MHz. It takes only 0.161s to complete a process of block of 88 samples. A frame of image is processed by the designed DCT unit and then reconstructed by the IDCT unit to verify the function. The Peak Signal to Noise Ratio (PSNR) can reach 51.99 dB.